TTL LRU LFU and Cache Memory Limits

04 Try it yourself Interactive

Trace an LRU cache

Read A, B, A, C, A, B. Compare capacity two with capacity three. The stage shows the whole order from least to most recently used.

Capacity 2

Small deterministic teaching model

Choose a preset, predict the outcome, then use Next, Back or Reset. No steps autoplay.

find key in cacheon miss: load, evict oldest if fullmove requested key to most-recent positionreturn value; count hit or miss

Press Next to work through it one step at a time.

Lookups–

Hits–

Misses–

Hit rate–

step 0 / 0